Bus Implementation Using New Low Power PFSCL Tristate Buffers
This paper proposes new positive feedback source coupled logic (PFSCL) tristate buffers suited to bus applications. The proposed buffers use switch to attain high impedance state and modify the load or the current source section. An interesting consequence of this is overall reduction in the power c...
Saved in:
Main Authors: | Neeta Pandey, Bharat Choudhary, Kirti Gupta, Ankit Mittal |
---|---|
Format: | Article |
Language: | English |
Published: |
Wiley
2016-01-01
|
Series: | Active and Passive Electronic Components |
Online Access: | http://dx.doi.org/10.1155/2016/4517292 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic
by: Kirti Gupta, et al.
Published: (2011-01-01) -
A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product
by: Kunwar Singh, et al.
Published: (2014-01-01) -
Gender-Inclusive Language in Public-Facing Labor and Delivery Web Pages in the New York Tristate Area: Cross-Sectional Study
by: Sarah Mohsen Isaac, et al.
Published: (2025-01-01) -
Static Switching Dynamic Buffer Circuit
by: A. K. Pandey, et al.
Published: (2013-01-01) -
A low-power metal–oxide scan driver circuit outputting non-overlapping pulses with DC power-supplied buffer
by: HyeongMin Kim, et al.
Published: (2025-01-01)