Bus Implementation Using New Low Power PFSCL Tristate Buffers
This paper proposes new positive feedback source coupled logic (PFSCL) tristate buffers suited to bus applications. The proposed buffers use switch to attain high impedance state and modify the load or the current source section. An interesting consequence of this is overall reduction in the power c...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2016-01-01
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| Series: | Active and Passive Electronic Components |
| Online Access: | http://dx.doi.org/10.1155/2016/4517292 |
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| author | Neeta Pandey Bharat Choudhary Kirti Gupta Ankit Mittal |
| author_facet | Neeta Pandey Bharat Choudhary Kirti Gupta Ankit Mittal |
| author_sort | Neeta Pandey |
| collection | DOAJ |
| description | This paper proposes new positive feedback source coupled logic (PFSCL) tristate buffers suited to bus applications. The proposed buffers use switch to attain high impedance state and modify the load or the current source section. An interesting consequence of this is overall reduction in the power consumption. The proposed tristate buffers consume half the power compared to the available switch based counterpart. The issues with available PFSCL tristate buffers based bus implementation are identified and benefits of employing the proposed tristate buffer topologies are put forward. SPICE simulation results using TSMC 180 nm CMOS technology parameters are included to support the theoretical formulations. The performance of proposed tristate buffer topologies is examined on the basis of propagation delay, output enable time, and power consumption. It is found that one of the proposed tristate buffer topology outperforms the others in terms of all the performance parameters. An examination of behavior of available and the proposed PFSCL tristate buffer topologies under parameter variations and mismatch shows a maximum variation of 14%. |
| format | Article |
| id | doaj-art-23b7f32d18af46058811f605588e86aa |
| institution | Kabale University |
| issn | 0882-7516 1563-5031 |
| language | English |
| publishDate | 2016-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Active and Passive Electronic Components |
| spelling | doaj-art-23b7f32d18af46058811f605588e86aa2025-02-03T01:11:45ZengWileyActive and Passive Electronic Components0882-75161563-50312016-01-01201610.1155/2016/45172924517292Bus Implementation Using New Low Power PFSCL Tristate BuffersNeeta Pandey0Bharat Choudhary1Kirti Gupta2Ankit Mittal3Department of Electronics and Communication Engineering, Delhi Technological University, Delhi 110042, IndiaDepartment of Electronics and Communication Engineering, Delhi Technological University, Delhi 110042, IndiaDepartment of Electronics and Communication Engineering, Bharati Vidyapeeth’s College of Engineering, Delhi 110063, IndiaDepartment of EEE/E&I, Birla Institute of Technology, Pilani University, K. K. Birla Goa Campus, Goa 403726, IndiaThis paper proposes new positive feedback source coupled logic (PFSCL) tristate buffers suited to bus applications. The proposed buffers use switch to attain high impedance state and modify the load or the current source section. An interesting consequence of this is overall reduction in the power consumption. The proposed tristate buffers consume half the power compared to the available switch based counterpart. The issues with available PFSCL tristate buffers based bus implementation are identified and benefits of employing the proposed tristate buffer topologies are put forward. SPICE simulation results using TSMC 180 nm CMOS technology parameters are included to support the theoretical formulations. The performance of proposed tristate buffer topologies is examined on the basis of propagation delay, output enable time, and power consumption. It is found that one of the proposed tristate buffer topology outperforms the others in terms of all the performance parameters. An examination of behavior of available and the proposed PFSCL tristate buffer topologies under parameter variations and mismatch shows a maximum variation of 14%.http://dx.doi.org/10.1155/2016/4517292 |
| spellingShingle | Neeta Pandey Bharat Choudhary Kirti Gupta Ankit Mittal Bus Implementation Using New Low Power PFSCL Tristate Buffers Active and Passive Electronic Components |
| title | Bus Implementation Using New Low Power PFSCL Tristate Buffers |
| title_full | Bus Implementation Using New Low Power PFSCL Tristate Buffers |
| title_fullStr | Bus Implementation Using New Low Power PFSCL Tristate Buffers |
| title_full_unstemmed | Bus Implementation Using New Low Power PFSCL Tristate Buffers |
| title_short | Bus Implementation Using New Low Power PFSCL Tristate Buffers |
| title_sort | bus implementation using new low power pfscl tristate buffers |
| url | http://dx.doi.org/10.1155/2016/4517292 |
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