Accelerating Deep Neural Networks implementation: A survey
Abstract Recently, Deep Learning (DL) applications are getting more and more involved in different fields. Deploying such Deep Neural Networks (DNN) on embedded devices is still a challenging task considering the massive requirement of computation and storage. Given that the number of operations and...
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| Format: | Article |
| Language: | English |
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Wiley
2021-03-01
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| Series: | IET Computers & Digital Techniques |
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| Online Access: | https://doi.org/10.1049/cdt2.12016 |
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| author | Meriam Dhouibi Ahmed Karim Ben Salem Afef Saidi Slim Ben Saoud |
| author_facet | Meriam Dhouibi Ahmed Karim Ben Salem Afef Saidi Slim Ben Saoud |
| author_sort | Meriam Dhouibi |
| collection | DOAJ |
| description | Abstract Recently, Deep Learning (DL) applications are getting more and more involved in different fields. Deploying such Deep Neural Networks (DNN) on embedded devices is still a challenging task considering the massive requirement of computation and storage. Given that the number of operations and parameters increases with the complexity of the model architecture, the performance will strongly depend on the hardware target resources and basically the memory footprint of the accelerator. Recent research studies have discussed the benefit of implementing some complex DL applications based on different models and platforms. However, it is necessary to guarantee the best performance when designing hardware accelerators for DL applications to run at full speed, despite the constraints of low power, high accuracy and throughput. Field Programmable Gate Arrays (FPGAs) are promising platforms for the deployment of large‐scale DNN which seek to reach a balance between the above objectives. Besides, the growing complexity of DL models has made researches think about applying optimization techniques to make them more hardware‐friendly. Herein, DL concept is presented. Then, a detailed description of different optimization techniques used in recent research works is explored. Finally, a survey of research works aiming to accelerate the implementation of DNN models on FPGAs is provided. |
| format | Article |
| id | doaj-art-2008560f7f9140fda729a41ab4b97207 |
| institution | Kabale University |
| issn | 1751-8601 1751-861X |
| language | English |
| publishDate | 2021-03-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Computers & Digital Techniques |
| spelling | doaj-art-2008560f7f9140fda729a41ab4b972072025-02-03T06:47:39ZengWileyIET Computers & Digital Techniques1751-86011751-861X2021-03-01152799610.1049/cdt2.12016Accelerating Deep Neural Networks implementation: A surveyMeriam Dhouibi0Ahmed Karim Ben Salem1Afef Saidi2Slim Ben Saoud3Advanced Systems Laboratory Tunisia Polytechnic School University of Carthage BP 743 La Marsa 2078 TunisiaAdvanced Systems Laboratory Tunisia Polytechnic School University of Carthage BP 743 La Marsa 2078 TunisiaAdvanced Systems Laboratory Tunisia Polytechnic School University of Carthage BP 743 La Marsa 2078 TunisiaAdvanced Systems Laboratory Tunisia Polytechnic School University of Carthage BP 743 La Marsa 2078 TunisiaAbstract Recently, Deep Learning (DL) applications are getting more and more involved in different fields. Deploying such Deep Neural Networks (DNN) on embedded devices is still a challenging task considering the massive requirement of computation and storage. Given that the number of operations and parameters increases with the complexity of the model architecture, the performance will strongly depend on the hardware target resources and basically the memory footprint of the accelerator. Recent research studies have discussed the benefit of implementing some complex DL applications based on different models and platforms. However, it is necessary to guarantee the best performance when designing hardware accelerators for DL applications to run at full speed, despite the constraints of low power, high accuracy and throughput. Field Programmable Gate Arrays (FPGAs) are promising platforms for the deployment of large‐scale DNN which seek to reach a balance between the above objectives. Besides, the growing complexity of DL models has made researches think about applying optimization techniques to make them more hardware‐friendly. Herein, DL concept is presented. Then, a detailed description of different optimization techniques used in recent research works is explored. Finally, a survey of research works aiming to accelerate the implementation of DNN models on FPGAs is provided.https://doi.org/10.1049/cdt2.12016field programmable gate arraysoptimisationdeep learning (artificial intelligence)hardware accelerators |
| spellingShingle | Meriam Dhouibi Ahmed Karim Ben Salem Afef Saidi Slim Ben Saoud Accelerating Deep Neural Networks implementation: A survey IET Computers & Digital Techniques field programmable gate arrays optimisation deep learning (artificial intelligence) hardware accelerators |
| title | Accelerating Deep Neural Networks implementation: A survey |
| title_full | Accelerating Deep Neural Networks implementation: A survey |
| title_fullStr | Accelerating Deep Neural Networks implementation: A survey |
| title_full_unstemmed | Accelerating Deep Neural Networks implementation: A survey |
| title_short | Accelerating Deep Neural Networks implementation: A survey |
| title_sort | accelerating deep neural networks implementation a survey |
| topic | field programmable gate arrays optimisation deep learning (artificial intelligence) hardware accelerators |
| url | https://doi.org/10.1049/cdt2.12016 |
| work_keys_str_mv | AT meriamdhouibi acceleratingdeepneuralnetworksimplementationasurvey AT ahmedkarimbensalem acceleratingdeepneuralnetworksimplementationasurvey AT afefsaidi acceleratingdeepneuralnetworksimplementationasurvey AT slimbensaoud acceleratingdeepneuralnetworksimplementationasurvey |