Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme
Abstract Digital data transmission is day by day more vulnerable to both malicious and natural faults. With an aim to assure reliability, security and privacy in communication, a low‐cost fault resilient architecture for Advanced Encryption Standard (AES) is proposed. In order not to degrade the rel...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2021-11-01
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| Series: | IET Computers & Digital Techniques |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cdt2.12031 |
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