Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme
Abstract Digital data transmission is day by day more vulnerable to both malicious and natural faults. With an aim to assure reliability, security and privacy in communication, a low‐cost fault resilient architecture for Advanced Encryption Standard (AES) is proposed. In order not to degrade the rel...
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| Format: | Article |
| Language: | English |
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Wiley
2021-11-01
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| Series: | IET Computers & Digital Techniques |
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| Online Access: | https://doi.org/10.1049/cdt2.12031 |
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| _version_ | 1832559676629188608 |
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| author | Saeideh Sheikhpur Mahdi Taheri Mohammad Saeed Ansari Ali Mahani |
| author_facet | Saeideh Sheikhpur Mahdi Taheri Mohammad Saeed Ansari Ali Mahani |
| author_sort | Saeideh Sheikhpur |
| collection | DOAJ |
| description | Abstract Digital data transmission is day by day more vulnerable to both malicious and natural faults. With an aim to assure reliability, security and privacy in communication, a low‐cost fault resilient architecture for Advanced Encryption Standard (AES) is proposed. In order not to degrade the reliability of our AES architecture, the reliability of voter is very important, for which reason we have introduced a novel voting scheme include a majority voter (named TMR voter) and an error barrier element (named DMR voter). In this paper, a reliable and secure 32‐bit data‐path AES implementation based on our robust fault resilient approach is developed. We illustrate that the proposed architecture can tolerate up to triple‐bit (byte) simultaneous faults at each pipeline stage’s logic and verify our claim through extensive error simulations. Error simulation results also show that our architecture achieves close to 100% fault‐masking capability for multiple‐bit (byte) faults. Finally, it is shown that the Application‐Specific Integrated Circuit implementation of the fault‐tolerant architectures using the composite field‐based S‐box, CFB‐AES, and ROM‐based S‐box, RB‐AES allows better area usage, throughput and fault resilience trade‐off compared to their counterparts. So, it provides the most appropriate features to be used in highly‐secure resource‐constraint applications. |
| format | Article |
| id | doaj-art-1f38511f7c97439181e00dfc41aa4492 |
| institution | Kabale University |
| issn | 1751-8601 1751-861X |
| language | English |
| publishDate | 2021-11-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Computers & Digital Techniques |
| spelling | doaj-art-1f38511f7c97439181e00dfc41aa44922025-02-03T01:29:24ZengWileyIET Computers & Digital Techniques1751-86011751-861X2021-11-0115639540810.1049/cdt2.12031Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting schemeSaeideh Sheikhpur0Mahdi Taheri1Mohammad Saeed Ansari2Ali Mahani3Reliable and Smart Systems (RSS) Lab., Department of Electrical Engineering Shahid Bahonar University of Kerman Kerman IranReliable and Smart Systems (RSS) Lab., Department of Electrical Engineering Shahid Bahonar University of Kerman Kerman IranEideticom Computational Storage Calgary Alberta CanadaReliable and Smart Systems (RSS) Lab., Department of Electrical Engineering Shahid Bahonar University of Kerman Kerman IranAbstract Digital data transmission is day by day more vulnerable to both malicious and natural faults. With an aim to assure reliability, security and privacy in communication, a low‐cost fault resilient architecture for Advanced Encryption Standard (AES) is proposed. In order not to degrade the reliability of our AES architecture, the reliability of voter is very important, for which reason we have introduced a novel voting scheme include a majority voter (named TMR voter) and an error barrier element (named DMR voter). In this paper, a reliable and secure 32‐bit data‐path AES implementation based on our robust fault resilient approach is developed. We illustrate that the proposed architecture can tolerate up to triple‐bit (byte) simultaneous faults at each pipeline stage’s logic and verify our claim through extensive error simulations. Error simulation results also show that our architecture achieves close to 100% fault‐masking capability for multiple‐bit (byte) faults. Finally, it is shown that the Application‐Specific Integrated Circuit implementation of the fault‐tolerant architectures using the composite field‐based S‐box, CFB‐AES, and ROM‐based S‐box, RB‐AES allows better area usage, throughput and fault resilience trade‐off compared to their counterparts. So, it provides the most appropriate features to be used in highly‐secure resource‐constraint applications.https://doi.org/10.1049/cdt2.12031cryptographyfield programmable gate arraysfault toleranceerror correctiontelecommunication securitydata communication |
| spellingShingle | Saeideh Sheikhpur Mahdi Taheri Mohammad Saeed Ansari Ali Mahani Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme IET Computers & Digital Techniques cryptography field programmable gate arrays fault tolerance error correction telecommunication security data communication |
| title | Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme |
| title_full | Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme |
| title_fullStr | Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme |
| title_full_unstemmed | Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme |
| title_short | Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme |
| title_sort | strengthened 32 bit aes implementation architectural error correction configuration with a new voting scheme |
| topic | cryptography field programmable gate arrays fault tolerance error correction telecommunication security data communication |
| url | https://doi.org/10.1049/cdt2.12031 |
| work_keys_str_mv | AT saeidehsheikhpur strengthened32bitaesimplementationarchitecturalerrorcorrectionconfigurationwithanewvotingscheme AT mahditaheri strengthened32bitaesimplementationarchitecturalerrorcorrectionconfigurationwithanewvotingscheme AT mohammadsaeedansari strengthened32bitaesimplementationarchitecturalerrorcorrectionconfigurationwithanewvotingscheme AT alimahani strengthened32bitaesimplementationarchitecturalerrorcorrectionconfigurationwithanewvotingscheme |