A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands
Buffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnect, and hence reducing them is an important problem. Application-specific designs have nonuniform network utilization, thereby requiring a buffer-sizing approach that tackles the nonuni...
Saved in:
| Main Authors: | , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2012-01-01
|
| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2012/537286 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832566263027597312 |
|---|---|
| author | Anish S. Kumar M. Pawan Kumar Srinivasan Murali V. Kamakoti Luca Benini Giovanni De Micheli |
| author_facet | Anish S. Kumar M. Pawan Kumar Srinivasan Murali V. Kamakoti Luca Benini Giovanni De Micheli |
| author_sort | Anish S. Kumar |
| collection | DOAJ |
| description | Buffers in on-chip networks constitute a significant
proportion of the power consumption and area of the
interconnect, and hence reducing them is an important problem.
Application-specific designs have nonuniform network
utilization, thereby requiring a buffer-sizing approach that
tackles the nonuniformity. Also, congestion effects that occur
during network operation need to be captured when sizing the
buffers. Many NoCs are designed to operate in multiple voltage/frequency islands, with interisland communication taking
place through frequency converters. To this end, we propose
a two-phase algorithm to size the switch buffers in network-on-chips (NoCs) considering support for multiple-frequency
islands. Our algorithm considers both the static and dynamic
effects when sizing buffers. We analyze the impact of placing
frequency converters (FCs) on a link, as well as pack and send
units that effectively utilize network bandwidth. Experiments
on many realistic system-on-Chip (SoC) benchmark show
that our algorithm results in 42% reduction in amount of
buffering when compared to a standard buffering approach. |
| format | Article |
| id | doaj-art-1eab157fc1e64830825c3756cad37721 |
| institution | Kabale University |
| issn | 2090-0147 2090-0155 |
| language | English |
| publishDate | 2012-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-1eab157fc1e64830825c3756cad377212025-02-03T01:04:36ZengWileyJournal of Electrical and Computer Engineering2090-01472090-01552012-01-01201210.1155/2012/537286537286A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency IslandsAnish S. Kumar0M. Pawan Kumar1Srinivasan Murali2V. Kamakoti3Luca Benini4Giovanni De Micheli5Indian Institute of Technology Madras, Chennai 600036, IndiaIndian Institute of Technology Madras, Chennai 600036, IndiaiNoCs, 1007 Lausanne, SwitzerlandIndian Institute of Technology Madras, Chennai 600036, IndiaUniversity of Bologna, 40138 Bologna, ItalyEPFL, 1015 Lausanne, SwitzerlandBuffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnect, and hence reducing them is an important problem. Application-specific designs have nonuniform network utilization, thereby requiring a buffer-sizing approach that tackles the nonuniformity. Also, congestion effects that occur during network operation need to be captured when sizing the buffers. Many NoCs are designed to operate in multiple voltage/frequency islands, with interisland communication taking place through frequency converters. To this end, we propose a two-phase algorithm to size the switch buffers in network-on-chips (NoCs) considering support for multiple-frequency islands. Our algorithm considers both the static and dynamic effects when sizing buffers. We analyze the impact of placing frequency converters (FCs) on a link, as well as pack and send units that effectively utilize network bandwidth. Experiments on many realistic system-on-Chip (SoC) benchmark show that our algorithm results in 42% reduction in amount of buffering when compared to a standard buffering approach.http://dx.doi.org/10.1155/2012/537286 |
| spellingShingle | Anish S. Kumar M. Pawan Kumar Srinivasan Murali V. Kamakoti Luca Benini Giovanni De Micheli A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands Journal of Electrical and Computer Engineering |
| title | A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands |
| title_full | A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands |
| title_fullStr | A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands |
| title_full_unstemmed | A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands |
| title_short | A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands |
| title_sort | buffer sizing algorithm for network on chips with multiple voltage frequency islands |
| url | http://dx.doi.org/10.1155/2012/537286 |
| work_keys_str_mv | AT anishskumar abuffersizingalgorithmfornetworkonchipswithmultiplevoltagefrequencyislands AT mpawankumar abuffersizingalgorithmfornetworkonchipswithmultiplevoltagefrequencyislands AT srinivasanmurali abuffersizingalgorithmfornetworkonchipswithmultiplevoltagefrequencyislands AT vkamakoti abuffersizingalgorithmfornetworkonchipswithmultiplevoltagefrequencyislands AT lucabenini abuffersizingalgorithmfornetworkonchipswithmultiplevoltagefrequencyislands AT giovannidemicheli abuffersizingalgorithmfornetworkonchipswithmultiplevoltagefrequencyislands AT anishskumar buffersizingalgorithmfornetworkonchipswithmultiplevoltagefrequencyislands AT mpawankumar buffersizingalgorithmfornetworkonchipswithmultiplevoltagefrequencyislands AT srinivasanmurali buffersizingalgorithmfornetworkonchipswithmultiplevoltagefrequencyislands AT vkamakoti buffersizingalgorithmfornetworkonchipswithmultiplevoltagefrequencyislands AT lucabenini buffersizingalgorithmfornetworkonchipswithmultiplevoltagefrequencyislands AT giovannidemicheli buffersizingalgorithmfornetworkonchipswithmultiplevoltagefrequencyislands |