A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands
Buffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnect, and hence reducing them is an important problem. Application-specific designs have nonuniform network utilization, thereby requiring a buffer-sizing approach that tackles the nonuni...
Saved in:
| Main Authors: | , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2012-01-01
|
| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2012/537286 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | Buffers in on-chip networks constitute a significant
proportion of the power consumption and area of the
interconnect, and hence reducing them is an important problem.
Application-specific designs have nonuniform network
utilization, thereby requiring a buffer-sizing approach that
tackles the nonuniformity. Also, congestion effects that occur
during network operation need to be captured when sizing the
buffers. Many NoCs are designed to operate in multiple voltage/frequency islands, with interisland communication taking
place through frequency converters. To this end, we propose
a two-phase algorithm to size the switch buffers in network-on-chips (NoCs) considering support for multiple-frequency
islands. Our algorithm considers both the static and dynamic
effects when sizing buffers. We analyze the impact of placing
frequency converters (FCs) on a link, as well as pack and send
units that effectively utilize network bandwidth. Experiments
on many realistic system-on-Chip (SoC) benchmark show
that our algorithm results in 42% reduction in amount of
buffering when compared to a standard buffering approach. |
|---|---|
| ISSN: | 2090-0147 2090-0155 |