A State-Based Modeling Approach for Efficient Performance Evaluation of Embedded System Architectures at Transaction Level
Abstract models are necessary to assist system architects in the evaluation process of hardware/software architectures and to cope with the still increasing complexity of embedded systems. Efficient methods are required to create reliable models of system architectures and to allow early performance...
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| Format: | Article |
| Language: | English |
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Wiley
2012-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2012/537327 |
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| author | Anthony Barreteau Sébastien Le Nours Olivier Pasquier |
| author_facet | Anthony Barreteau Sébastien Le Nours Olivier Pasquier |
| author_sort | Anthony Barreteau |
| collection | DOAJ |
| description | Abstract models are necessary to assist system architects in the evaluation process of hardware/software architectures and to cope with the still increasing complexity of embedded systems. Efficient methods are required to create reliable models of system architectures and to allow early performance evaluation and fast exploration of the design space. In this paper, we present a specific transaction level modeling approach for performance evaluation of hardware/software architectures. This approach relies on a generic execution model that exhibits light modeling effort. Created models are used to evaluate by simulation expected processing and memory resources according to various architectures. The proposed execution model relies on a specific computation method defined to improve the simulation speed of transaction level models. The benefits of the proposed approach are highlighted through two case studies. The first case study is a didactic example illustrating the modeling approach. In this example, a simulation speed-up by a factor of 7,62 is achieved by using the proposed computation method. The second case study concerns the analysis of a communication receiver supporting part of the physical layer of the LTE protocol. In this case study, architecture exploration is led in order to improve the allocation of processing functions. |
| format | Article |
| id | doaj-art-1d523ff06cae43ecbbf1af613d71663b |
| institution | Kabale University |
| issn | 2090-0147 2090-0155 |
| language | English |
| publishDate | 2012-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-1d523ff06cae43ecbbf1af613d71663b2025-08-20T03:54:38ZengWileyJournal of Electrical and Computer Engineering2090-01472090-01552012-01-01201210.1155/2012/537327537327A State-Based Modeling Approach for Efficient Performance Evaluation of Embedded System Architectures at Transaction LevelAnthony Barreteau0Sébastien Le Nours1Olivier Pasquier2IREENA, EA1770, Université de Nantes, Polytech-Nantes, rue C. Pauc, Bât. IRESTE, BP 50609, 44000 Nantes, FranceIREENA, EA1770, Université de Nantes, Polytech-Nantes, rue C. Pauc, Bât. IRESTE, BP 50609, 44000 Nantes, FranceIREENA, EA1770, Université de Nantes, Polytech-Nantes, rue C. Pauc, Bât. IRESTE, BP 50609, 44000 Nantes, FranceAbstract models are necessary to assist system architects in the evaluation process of hardware/software architectures and to cope with the still increasing complexity of embedded systems. Efficient methods are required to create reliable models of system architectures and to allow early performance evaluation and fast exploration of the design space. In this paper, we present a specific transaction level modeling approach for performance evaluation of hardware/software architectures. This approach relies on a generic execution model that exhibits light modeling effort. Created models are used to evaluate by simulation expected processing and memory resources according to various architectures. The proposed execution model relies on a specific computation method defined to improve the simulation speed of transaction level models. The benefits of the proposed approach are highlighted through two case studies. The first case study is a didactic example illustrating the modeling approach. In this example, a simulation speed-up by a factor of 7,62 is achieved by using the proposed computation method. The second case study concerns the analysis of a communication receiver supporting part of the physical layer of the LTE protocol. In this case study, architecture exploration is led in order to improve the allocation of processing functions.http://dx.doi.org/10.1155/2012/537327 |
| spellingShingle | Anthony Barreteau Sébastien Le Nours Olivier Pasquier A State-Based Modeling Approach for Efficient Performance Evaluation of Embedded System Architectures at Transaction Level Journal of Electrical and Computer Engineering |
| title | A State-Based Modeling Approach for Efficient Performance Evaluation of Embedded System Architectures at Transaction Level |
| title_full | A State-Based Modeling Approach for Efficient Performance Evaluation of Embedded System Architectures at Transaction Level |
| title_fullStr | A State-Based Modeling Approach for Efficient Performance Evaluation of Embedded System Architectures at Transaction Level |
| title_full_unstemmed | A State-Based Modeling Approach for Efficient Performance Evaluation of Embedded System Architectures at Transaction Level |
| title_short | A State-Based Modeling Approach for Efficient Performance Evaluation of Embedded System Architectures at Transaction Level |
| title_sort | state based modeling approach for efficient performance evaluation of embedded system architectures at transaction level |
| url | http://dx.doi.org/10.1155/2012/537327 |
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