Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics
FPGA design of side-channel analysis countermeasures using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing whereas both FPGA layout and FPGA EDA tools are not developed for such pu...
Saved in:
| Main Authors: | , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2010-01-01
|
| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2010/375245 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832552757807022080 |
|---|---|
| author | Laurent Sauvage Maxime Nassar Sylvain Guilley Florent Flament Jean-Luc Danger Yves Mathieu |
| author_facet | Laurent Sauvage Maxime Nassar Sylvain Guilley Florent Flament Jean-Luc Danger Yves Mathieu |
| author_sort | Laurent Sauvage |
| collection | DOAJ |
| description | FPGA design of side-channel analysis countermeasures using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing whereas both FPGA layout and FPGA EDA tools are not developed
for such purposes. However, assessing the security level which can be achieved with them is an important issue, as it is directly related to the suitability to use commercial FPGA instead of proprietary custom FPGA for this kind of protection. In this article, we experimentally gave evidence that differential placement and routing of an FPGA implementation can be done with a granularity fine enough to improve the security gain. However, so far, this gain turned out to be lower for FPGAs than for ASICs. The solutions demonstrated in this article exploit the dual-output of modern FPGAs to achieve a better balance of dual-rail interconnections. However, we expect that an in-depth analysis of routing resources power consumption could still help reduce the interconnect differential leakage. |
| format | Article |
| id | doaj-art-1ced2e3eda574016927792d179e66295 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2010-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-1ced2e3eda574016927792d179e662952025-02-03T05:57:45ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092010-01-01201010.1155/2010/375245375245Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail LogicsLaurent Sauvage0Maxime Nassar1Sylvain Guilley2Florent Flament3Jean-Luc Danger4Yves Mathieu5Département COMELEC, Institut TELECOM/TELECOM ParisTech, CNRS LTCI (UMR 5141), 46 Rue Barrault, 75 634 Paris Cedex 13, FranceDépartement COMELEC, Institut TELECOM/TELECOM ParisTech, CNRS LTCI (UMR 5141), 46 Rue Barrault, 75 634 Paris Cedex 13, FranceDépartement COMELEC, Institut TELECOM/TELECOM ParisTech, CNRS LTCI (UMR 5141), 46 Rue Barrault, 75 634 Paris Cedex 13, FranceDépartement COMELEC, Institut TELECOM/TELECOM ParisTech, CNRS LTCI (UMR 5141), 46 Rue Barrault, 75 634 Paris Cedex 13, FranceDépartement COMELEC, Institut TELECOM/TELECOM ParisTech, CNRS LTCI (UMR 5141), 46 Rue Barrault, 75 634 Paris Cedex 13, FranceDépartement COMELEC, Institut TELECOM/TELECOM ParisTech, CNRS LTCI (UMR 5141), 46 Rue Barrault, 75 634 Paris Cedex 13, FranceFPGA design of side-channel analysis countermeasures using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing whereas both FPGA layout and FPGA EDA tools are not developed for such purposes. However, assessing the security level which can be achieved with them is an important issue, as it is directly related to the suitability to use commercial FPGA instead of proprietary custom FPGA for this kind of protection. In this article, we experimentally gave evidence that differential placement and routing of an FPGA implementation can be done with a granularity fine enough to improve the security gain. However, so far, this gain turned out to be lower for FPGAs than for ASICs. The solutions demonstrated in this article exploit the dual-output of modern FPGAs to achieve a better balance of dual-rail interconnections. However, we expect that an in-depth analysis of routing resources power consumption could still help reduce the interconnect differential leakage.http://dx.doi.org/10.1155/2010/375245 |
| spellingShingle | Laurent Sauvage Maxime Nassar Sylvain Guilley Florent Flament Jean-Luc Danger Yves Mathieu Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics International Journal of Reconfigurable Computing |
| title | Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics |
| title_full | Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics |
| title_fullStr | Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics |
| title_full_unstemmed | Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics |
| title_short | Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics |
| title_sort | exploiting dual output programmable blocks to balance secure dual rail logics |
| url | http://dx.doi.org/10.1155/2010/375245 |
| work_keys_str_mv | AT laurentsauvage exploitingdualoutputprogrammableblockstobalancesecuredualraillogics AT maximenassar exploitingdualoutputprogrammableblockstobalancesecuredualraillogics AT sylvainguilley exploitingdualoutputprogrammableblockstobalancesecuredualraillogics AT florentflament exploitingdualoutputprogrammableblockstobalancesecuredualraillogics AT jeanlucdanger exploitingdualoutputprogrammableblockstobalancesecuredualraillogics AT yvesmathieu exploitingdualoutputprogrammableblockstobalancesecuredualraillogics |