Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics Applications
System considerations, circuit architecture, and design implementation of wireline and linear optics transceivers capable of supporting data-rates beyond 200 Gb/s are presented. We showcase the silicon results of a transceiver designed in the advanced 3-nm CMOS process, which supports long-reach cha...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10756610/ |
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| author | Ahmad Khairi Amir Laufer Ilia Radashkevich Yoel Krupnik Jihwan Kim Tali Warshavsky Grafi Ajay Balankutty Yaniv Sabag Yoav Segal Udi Virobnik Mike Peng Li Itamar Levin Yosef Ben Ezra Ariel Cohen |
| author_facet | Ahmad Khairi Amir Laufer Ilia Radashkevich Yoel Krupnik Jihwan Kim Tali Warshavsky Grafi Ajay Balankutty Yaniv Sabag Yoav Segal Udi Virobnik Mike Peng Li Itamar Levin Yosef Ben Ezra Ariel Cohen |
| author_sort | Ahmad Khairi |
| collection | DOAJ |
| description | System considerations, circuit architecture, and design implementation of wireline and linear optics transceivers capable of supporting data-rates beyond 200 Gb/s are presented. We showcase the silicon results of a transceiver designed in the advanced 3-nm CMOS process, which supports long-reach channels with up to 40 dB of loss at Nyquist. These results demonstrate the technology’s benefits of doubling the data rate of transceivers while achieving efficiency gains in power consumption and silicon area. This article highlights several key circuits architecture, such as hybrid continuous-time linear equalizer, inductive peaking clock routing, and one stage TX driver based on grounded switches. The proof-of-concept demonstration of 224 Gb/s with linear optics opens the avenue for power-efficient, low-latency future optical communication. This is crucial for high-performance computing (HPC) networking as well as emerging applications in high-end FPGA. |
| format | Article |
| id | doaj-art-1a61bad89f914316847e29265c5dbfa5 |
| institution | Kabale University |
| issn | 2644-1349 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj-art-1a61bad89f914316847e29265c5dbfa52025-01-25T00:03:09ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492024-01-01426527610.1109/OJSSCS.2024.350197510756610Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics ApplicationsAhmad Khairi0https://orcid.org/0000-0001-7490-1037Amir Laufer1Ilia Radashkevich2Yoel Krupnik3https://orcid.org/0000-0002-0724-8389Jihwan Kim4https://orcid.org/0000-0002-5599-2997Tali Warshavsky Grafi5Ajay Balankutty6Yaniv Sabag7Yoav Segal8Udi Virobnik9Mike Peng Li10Itamar Levin11https://orcid.org/0000-0002-3421-8193Yosef Ben Ezra12Ariel Cohen13Intel Corporation, Santa Clara, CA, USAIntel Corporation, Santa Clara, CA, USAIntel Corporation, Santa Clara, CA, USAIntel Corporation, Santa Clara, CA, USAIntel Corporation, Santa Clara, CA, USAIntel Corporation, Santa Clara, CA, USAIntel Corporation, Santa Clara, CA, USAIntel Corporation, Santa Clara, CA, USAIntel Corporation, Santa Clara, CA, USAIntel Corporation, Santa Clara, CA, USAIntel Corporation, Santa Clara, CA, USAIntel Corporation, Santa Clara, CA, USAFaculty of Electric and Electronics Engineering, Holon Institute of Technology, Holon, IsraelIntel Corporation, Santa Clara, CA, USASystem considerations, circuit architecture, and design implementation of wireline and linear optics transceivers capable of supporting data-rates beyond 200 Gb/s are presented. We showcase the silicon results of a transceiver designed in the advanced 3-nm CMOS process, which supports long-reach channels with up to 40 dB of loss at Nyquist. These results demonstrate the technology’s benefits of doubling the data rate of transceivers while achieving efficiency gains in power consumption and silicon area. This article highlights several key circuits architecture, such as hybrid continuous-time linear equalizer, inductive peaking clock routing, and one stage TX driver based on grounded switches. The proof-of-concept demonstration of 224 Gb/s with linear optics opens the avenue for power-efficient, low-latency future optical communication. This is crucial for high-performance computing (HPC) networking as well as emerging applications in high-end FPGA.https://ieeexplore.ieee.org/document/10756610/224 Gb/s3 nmdigital DFE PLLdigital feed-forward equalizer (FFE)direct drive linear opticselectro-optics |
| spellingShingle | Ahmad Khairi Amir Laufer Ilia Radashkevich Yoel Krupnik Jihwan Kim Tali Warshavsky Grafi Ajay Balankutty Yaniv Sabag Yoav Segal Udi Virobnik Mike Peng Li Itamar Levin Yosef Ben Ezra Ariel Cohen Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics Applications IEEE Open Journal of the Solid-State Circuits Society 224 Gb/s 3 nm digital DFE PLL digital feed-forward equalizer (FFE) direct drive linear optics electro-optics |
| title | Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics Applications |
| title_full | Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics Applications |
| title_fullStr | Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics Applications |
| title_full_unstemmed | Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics Applications |
| title_short | Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics Applications |
| title_sort | beyond 200 gb s pam4 adc and dac based transceiver for wireline and linear optics applications |
| topic | 224 Gb/s 3 nm digital DFE PLL digital feed-forward equalizer (FFE) direct drive linear optics electro-optics |
| url | https://ieeexplore.ieee.org/document/10756610/ |
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