Optimization of PLL frequency synthesizer
The influence of different configurations of phase-locked loop frequency (PLL) with integer coefficients on parameters of the PLL loop of the frequency synthesizer is considered. The possibility of computer prediction of such PLL parameters as power consumption, start-up time, jitter and phase n...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Omsk State Technical University, Federal State Autonoumos Educational Institution of Higher Education
2019-06-01
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| Series: | Омский научный вестник |
| Subjects: | |
| Online Access: | https://www.omgtu.ru/general_information/media_omgtu/journal_of_omsk_research_journal/files/arhiv/2019/3%20(165)/28-32%20%D0%9A%D0%BE%D1%89%D1%83%D0%BA%20%D0%93.%20%D0%90.,%20%D0%A2%D0%B8%D1%85%D0%BE%D0%BD%D0%BE%D0%B2%20%D0%98.%20%D0%90.,%20%D0%9A%D0%BE%D1%81%D0%B0%D1%80%D0%B5%D0%B2%20%D0%91.%20%D0%90..pdf |
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| Summary: | The influence of different configurations of phase-locked loop
frequency (PLL) with integer coefficients on parameters of
the PLL loop of the frequency synthesizer is considered. The
possibility of computer prediction of such PLL parameters as
power consumption, start-up time, jitter and phase noise level
at the choice of the frequency divider from the generator to
the circuit output is shown. |
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| ISSN: | 1813-8225 2541-7541 |