Applying Partial Power-Gating to Direction-Sliced Network-on-Chip
Network-on-Chip (NoC) is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve t...
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| Format: | Article |
| Language: | English |
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Wiley
2015-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2015/862387 |
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| _version_ | 1832558912756252672 |
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| author | Feng Wang Xiantuo Tang Zuocheng Xing |
| author_facet | Feng Wang Xiantuo Tang Zuocheng Xing |
| author_sort | Feng Wang |
| collection | DOAJ |
| description | Network-on-Chip (NoC) is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis. However, the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper, we propose a novel partial power-gating approach to improve the performance in the power-gated NoC. The approach mainly involves a direction-slicing scheme, an improved routing algorithm, and a deadlock recovery mechanism. In the synthetic traffic simulation, the proposed design shows favorable power-efficiency at low-load range and achieves better performance than the conventional power-gated one. For the application trace simulation, the design in the mesh/torus network consumes 15.2%/18.9% more power on average, whereas it can averagely obtain 45.0%/28.7% performance improvement compared with the conventional power-gated design. On balance, the proposed design with partial power-gating has a better tradeoff between performance and power-efficiency. |
| format | Article |
| id | doaj-art-174c03350c294d6da2a67d3a3f227f2e |
| institution | Kabale University |
| issn | 2090-0147 2090-0155 |
| language | English |
| publishDate | 2015-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-174c03350c294d6da2a67d3a3f227f2e2025-02-03T01:31:17ZengWileyJournal of Electrical and Computer Engineering2090-01472090-01552015-01-01201510.1155/2015/862387862387Applying Partial Power-Gating to Direction-Sliced Network-on-ChipFeng Wang0Xiantuo Tang1Zuocheng Xing2National Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha 410073, ChinaNational Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha 410073, ChinaNational Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha 410073, ChinaNetwork-on-Chip (NoC) is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis. However, the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper, we propose a novel partial power-gating approach to improve the performance in the power-gated NoC. The approach mainly involves a direction-slicing scheme, an improved routing algorithm, and a deadlock recovery mechanism. In the synthetic traffic simulation, the proposed design shows favorable power-efficiency at low-load range and achieves better performance than the conventional power-gated one. For the application trace simulation, the design in the mesh/torus network consumes 15.2%/18.9% more power on average, whereas it can averagely obtain 45.0%/28.7% performance improvement compared with the conventional power-gated design. On balance, the proposed design with partial power-gating has a better tradeoff between performance and power-efficiency.http://dx.doi.org/10.1155/2015/862387 |
| spellingShingle | Feng Wang Xiantuo Tang Zuocheng Xing Applying Partial Power-Gating to Direction-Sliced Network-on-Chip Journal of Electrical and Computer Engineering |
| title | Applying Partial Power-Gating to Direction-Sliced Network-on-Chip |
| title_full | Applying Partial Power-Gating to Direction-Sliced Network-on-Chip |
| title_fullStr | Applying Partial Power-Gating to Direction-Sliced Network-on-Chip |
| title_full_unstemmed | Applying Partial Power-Gating to Direction-Sliced Network-on-Chip |
| title_short | Applying Partial Power-Gating to Direction-Sliced Network-on-Chip |
| title_sort | applying partial power gating to direction sliced network on chip |
| url | http://dx.doi.org/10.1155/2015/862387 |
| work_keys_str_mv | AT fengwang applyingpartialpowergatingtodirectionslicednetworkonchip AT xiantuotang applyingpartialpowergatingtodirectionslicednetworkonchip AT zuochengxing applyingpartialpowergatingtodirectionslicednetworkonchip |