PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability
Packet classification plays a crucial role for a number of network services such as policy-based routing, firewalls, and traffic billing, to name a few. However, classification can be a bottleneck in the above-mentioned applications if not implemented properly and efficiently. In this paper, we prop...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2011-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2011/648483 |
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| _version_ | 1832564243891748864 |
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| author | O. Ahmed S. Areibi K. Chattha B. Kelly |
| author_facet | O. Ahmed S. Areibi K. Chattha B. Kelly |
| author_sort | O. Ahmed |
| collection | DOAJ |
| description | Packet classification plays a crucial role for a number of network services such as policy-based routing, firewalls, and traffic billing, to name a few. However, classification can be a bottleneck in the above-mentioned applications if not implemented properly and efficiently. In this paper, we propose PCIU, a novel classification algorithm, which improves upon previously published work. PCIU provides lower preprocessing time, lower memory consumption, ease of incremental rule update, and reasonable classification time compared to state-of-the-art algorithms. The proposed algorithm was evaluated and compared to RFC and HiCut using several benchmarks. Results obtained indicate that PCIU outperforms these algorithms in terms of speed, memory usage, incremental update capability, and preprocessing time. The algorithm, furthermore, was improved and made more accessible for a variety of applications through implementation in hardware. Two such implementations are detailed and discussed in this paper. The results indicate that a hardware/software codesign approach results in a slower, but easier to optimize and improve within time constraints, PCIU solution. A hardware accelerator based on an ESL approach using Handel-C, on the other hand, resulted in a 31x speed-up over a pure software implementation running on a state of the art Xeon processor. |
| format | Article |
| id | doaj-art-1705b311a8c34befa58263b278d30020 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2011-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-1705b311a8c34befa58263b278d300202025-02-03T01:11:25ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092011-01-01201110.1155/2011/648483648483PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update CapabilityO. Ahmed0S. Areibi1K. Chattha2B. Kelly3School of Engineering, University of Guelph, Guelph, ON, N1G 2W1, CanadaSchool of Engineering, University of Guelph, Guelph, ON, N1G 2W1, CanadaSchool of Engineering, University of Guelph, Guelph, ON, N1G 2W1, CanadaSchool of Engineering, University of Guelph, Guelph, ON, N1G 2W1, CanadaPacket classification plays a crucial role for a number of network services such as policy-based routing, firewalls, and traffic billing, to name a few. However, classification can be a bottleneck in the above-mentioned applications if not implemented properly and efficiently. In this paper, we propose PCIU, a novel classification algorithm, which improves upon previously published work. PCIU provides lower preprocessing time, lower memory consumption, ease of incremental rule update, and reasonable classification time compared to state-of-the-art algorithms. The proposed algorithm was evaluated and compared to RFC and HiCut using several benchmarks. Results obtained indicate that PCIU outperforms these algorithms in terms of speed, memory usage, incremental update capability, and preprocessing time. The algorithm, furthermore, was improved and made more accessible for a variety of applications through implementation in hardware. Two such implementations are detailed and discussed in this paper. The results indicate that a hardware/software codesign approach results in a slower, but easier to optimize and improve within time constraints, PCIU solution. A hardware accelerator based on an ESL approach using Handel-C, on the other hand, resulted in a 31x speed-up over a pure software implementation running on a state of the art Xeon processor.http://dx.doi.org/10.1155/2011/648483 |
| spellingShingle | O. Ahmed S. Areibi K. Chattha B. Kelly PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability International Journal of Reconfigurable Computing |
| title | PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability |
| title_full | PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability |
| title_fullStr | PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability |
| title_full_unstemmed | PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability |
| title_short | PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability |
| title_sort | pciu hardware implementations of an efficient packet classification algorithm with an incremental update capability |
| url | http://dx.doi.org/10.1155/2011/648483 |
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