Speeding Up FPGA Placement via Partitioning and Multithreading
One of the current main challenges of the FPGA design flow is the long processing time of the placement and routing algorithms. In this paper, we propose a hybrid parallelization technique of the simulated annealing-based placement algorithm of VPR developed in the work of Betz and Rose (1997). The...
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| Format: | Article |
| Language: | English |
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Wiley
2009-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2009/514754 |
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| _version_ | 1832545557377187840 |
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| author | Cristinel Ababei |
| author_facet | Cristinel Ababei |
| author_sort | Cristinel Ababei |
| collection | DOAJ |
| description | One of the current main challenges of the FPGA design flow is the long processing time of the placement and routing algorithms. In this paper, we propose a hybrid parallelization technique of the simulated annealing-based placement algorithm of VPR developed in the work of Betz and Rose (1997). The proposed technique uses balanced region-based partitioning and multithreading. In the first step of this approach
placement subproblems are created by partitioning and then processed concurrently by multiple worker threads that are run on multiple cores of the same processor. Our main goal is to investigate the speedup that can be achieved with this simple approach compared to previous approaches that were based on distributed computing. The new hybrid parallel placement algorithm achieves an average speedup of 2.5× using four worker threads, while the total wire length and circuit delay after routing are minimally degraded. |
| format | Article |
| id | doaj-art-13c2c2b2b75248018cb9325551e34be2 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2009-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-13c2c2b2b75248018cb9325551e34be22025-02-03T07:25:25ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092009-01-01200910.1155/2009/514754514754Speeding Up FPGA Placement via Partitioning and MultithreadingCristinel Ababei0Electrical and Computer Engineering, North Dakota State University, Fargo, ND 58108-6050, USAOne of the current main challenges of the FPGA design flow is the long processing time of the placement and routing algorithms. In this paper, we propose a hybrid parallelization technique of the simulated annealing-based placement algorithm of VPR developed in the work of Betz and Rose (1997). The proposed technique uses balanced region-based partitioning and multithreading. In the first step of this approach placement subproblems are created by partitioning and then processed concurrently by multiple worker threads that are run on multiple cores of the same processor. Our main goal is to investigate the speedup that can be achieved with this simple approach compared to previous approaches that were based on distributed computing. The new hybrid parallel placement algorithm achieves an average speedup of 2.5× using four worker threads, while the total wire length and circuit delay after routing are minimally degraded.http://dx.doi.org/10.1155/2009/514754 |
| spellingShingle | Cristinel Ababei Speeding Up FPGA Placement via Partitioning and Multithreading International Journal of Reconfigurable Computing |
| title | Speeding Up FPGA Placement via Partitioning and Multithreading |
| title_full | Speeding Up FPGA Placement via Partitioning and Multithreading |
| title_fullStr | Speeding Up FPGA Placement via Partitioning and Multithreading |
| title_full_unstemmed | Speeding Up FPGA Placement via Partitioning and Multithreading |
| title_short | Speeding Up FPGA Placement via Partitioning and Multithreading |
| title_sort | speeding up fpga placement via partitioning and multithreading |
| url | http://dx.doi.org/10.1155/2009/514754 |
| work_keys_str_mv | AT cristinelababei speedingupfpgaplacementviapartitioningandmultithreading |