FASQuiC: Flexible Architecture for Scalable Spin Qubit Control
As scaling becomes a key issue for large-scale quantum computing, hardware control systems will become increasingly costly in resources. This article presents a compact direct digital synthesis architecture for signal generation adapted for spin qubits that is scalable in terms of waveform accuracy...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Transactions on Quantum Engineering |
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| Online Access: | https://ieeexplore.ieee.org/document/10549805/ |
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| author | Mathieu Toubeix Eric Guthmuller Adrian Evans Antoine Faurie Tristan Meunier |
| author_facet | Mathieu Toubeix Eric Guthmuller Adrian Evans Antoine Faurie Tristan Meunier |
| author_sort | Mathieu Toubeix |
| collection | DOAJ |
| description | As scaling becomes a key issue for large-scale quantum computing, hardware control systems will become increasingly costly in resources. This article presents a compact direct digital synthesis architecture for signal generation adapted for spin qubits that is scalable in terms of waveform accuracy and the number of synchronized channels. The architecture can produce programmable combinations of ramps, frequency combs, and arbitrary waveform generation (AWG) at 5 GS/s, with a worst-case digital feedback latency of 76.8 ns. The field-programmable gate array (FPGA)-based system is highly configurable and takes advantage of bitstream switching to achieve the high flexibility required for scalable calibration. The architecture also provides GHz rate, multiplexed, in-phase and quadrature component, single-side band modulation for scalable reflectometry. This architecture has been validated in hardware on a Xilinx ZCU111 FPGA demonstrating the mixing of complex signals and the quality of the frequency comb generation for multiplexed control and measurement. The key benefits of this design are the increase of controllability of ramps at the digital-to-analog converter (DAC) frequency and the reduction in memory requirements by several orders of magnitude compared with existing AWG-based architectures. The hardware for a single channel is very compact, 2% of ZCU111 logic resources for one DAC lane in the default configuration, leaving significant circuit resources for integrated feedback, calibration, and quantum error correction. |
| format | Article |
| id | doaj-art-103693d2f4b94da3b1633b421dcafd54 |
| institution | Kabale University |
| issn | 2689-1808 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Transactions on Quantum Engineering |
| spelling | doaj-art-103693d2f4b94da3b1633b421dcafd542025-01-25T00:03:33ZengIEEEIEEE Transactions on Quantum Engineering2689-18082024-01-01511610.1109/TQE.2024.340981110549805FASQuiC: Flexible Architecture for Scalable Spin Qubit ControlMathieu Toubeix0https://orcid.org/0009-0006-7830-4313Eric Guthmuller1https://orcid.org/0009-0002-0678-7599Adrian Evans2https://orcid.org/0000-0002-2617-5007Antoine Faurie3https://orcid.org/0009-0007-2572-360XTristan Meunier4CEA, List, Université Grenoble Alpes, Grenoble, FranceCNRS, Institut Néel, Université Grenoble Alpes, Grenoble, FranceCNRS, Institut Néel, Université Grenoble Alpes, Grenoble, FranceCNRS, Institut Néel, Université Grenoble Alpes, Grenoble, FranceCNRS, Institut Néel, Université Grenoble Alpes, Grenoble, FranceAs scaling becomes a key issue for large-scale quantum computing, hardware control systems will become increasingly costly in resources. This article presents a compact direct digital synthesis architecture for signal generation adapted for spin qubits that is scalable in terms of waveform accuracy and the number of synchronized channels. The architecture can produce programmable combinations of ramps, frequency combs, and arbitrary waveform generation (AWG) at 5 GS/s, with a worst-case digital feedback latency of 76.8 ns. The field-programmable gate array (FPGA)-based system is highly configurable and takes advantage of bitstream switching to achieve the high flexibility required for scalable calibration. The architecture also provides GHz rate, multiplexed, in-phase and quadrature component, single-side band modulation for scalable reflectometry. This architecture has been validated in hardware on a Xilinx ZCU111 FPGA demonstrating the mixing of complex signals and the quality of the frequency comb generation for multiplexed control and measurement. The key benefits of this design are the increase of controllability of ramps at the digital-to-analog converter (DAC) frequency and the reduction in memory requirements by several orders of magnitude compared with existing AWG-based architectures. The hardware for a single channel is very compact, 2% of ZCU111 logic resources for one DAC lane in the default configuration, leaving significant circuit resources for integrated feedback, calibration, and quantum error correction.https://ieeexplore.ieee.org/document/10549805/Direct digital synthesisfield-programmable gate array (FPGA)large-scale quantum (LSQ) computingquantum controlspin qubits |
| spellingShingle | Mathieu Toubeix Eric Guthmuller Adrian Evans Antoine Faurie Tristan Meunier FASQuiC: Flexible Architecture for Scalable Spin Qubit Control IEEE Transactions on Quantum Engineering Direct digital synthesis field-programmable gate array (FPGA) large-scale quantum (LSQ) computing quantum control spin qubits |
| title | FASQuiC: Flexible Architecture for Scalable Spin Qubit Control |
| title_full | FASQuiC: Flexible Architecture for Scalable Spin Qubit Control |
| title_fullStr | FASQuiC: Flexible Architecture for Scalable Spin Qubit Control |
| title_full_unstemmed | FASQuiC: Flexible Architecture for Scalable Spin Qubit Control |
| title_short | FASQuiC: Flexible Architecture for Scalable Spin Qubit Control |
| title_sort | fasquic flexible architecture for scalable spin qubit control |
| topic | Direct digital synthesis field-programmable gate array (FPGA) large-scale quantum (LSQ) computing quantum control spin qubits |
| url | https://ieeexplore.ieee.org/document/10549805/ |
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