Multi-Level Cell Structure for Capacitor-Less 1T DRAM With SiGe-Based Separated Data Storing Regions
One-transistor dynamic random-access memory (1T DRAM) offers significant advantages in fabrication process and scalability over the traditional one-transistor one-capacitor (1T-1C) DRAM due to its simplified structure that eliminates the need for capacitors. However, a limitation arises from its sin...
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IEEE
2025-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10937212/ |
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| author | Eungi Hwang Jang Hyun Kim Sangwan Kim Garam Kim |
| author_facet | Eungi Hwang Jang Hyun Kim Sangwan Kim Garam Kim |
| author_sort | Eungi Hwang |
| collection | DOAJ |
| description | One-transistor dynamic random-access memory (1T DRAM) offers significant advantages in fabrication process and scalability over the traditional one-transistor one-capacitor (1T-1C) DRAM due to its simplified structure that eliminates the need for capacitors. However, a limitation arises from its single-bit data storage capability, which necessitates scaling down to improve integration density. In this paper, we propose a multi-level cell structure for 1T DRAM to overcome and improve upon these limitations. Through technology computer-aided design (TCAD) simulations, the memory operation of the proposed device is validated, and it is confirmed that using Si0.8Ge0.2 in the data storing region significantly enhances the sensing margin compared to Si. Additionally, the proposed structure is shown to offer advantages over the conventional structure in terms of current variation. |
| format | Article |
| id | doaj-art-0e8764fe1dcf4e2fb3a6dccc8a534308 |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-0e8764fe1dcf4e2fb3a6dccc8a5343082025-08-20T03:42:18ZengIEEEIEEE Access2169-35362025-01-0113525285253710.1109/ACCESS.2025.355380210937212Multi-Level Cell Structure for Capacitor-Less 1T DRAM With SiGe-Based Separated Data Storing RegionsEungi Hwang0https://orcid.org/0009-0007-7086-9616Jang Hyun Kim1https://orcid.org/0000-0002-5936-4314Sangwan Kim2https://orcid.org/0000-0002-6492-7740Garam Kim3https://orcid.org/0000-0001-6517-7120Department of Electronic Engineering, Myongji University, Yongin, South KoreaDepartment of Intelligent Semiconductor Engineering, Ajou University, Suwon, South KoreaDepartment of Electronic Engineering, Sogang University, Seoul, South KoreaDepartment of Electronic Engineering, Myongji University, Yongin, South KoreaOne-transistor dynamic random-access memory (1T DRAM) offers significant advantages in fabrication process and scalability over the traditional one-transistor one-capacitor (1T-1C) DRAM due to its simplified structure that eliminates the need for capacitors. However, a limitation arises from its single-bit data storage capability, which necessitates scaling down to improve integration density. In this paper, we propose a multi-level cell structure for 1T DRAM to overcome and improve upon these limitations. Through technology computer-aided design (TCAD) simulations, the memory operation of the proposed device is validated, and it is confirmed that using Si0.8Ge0.2 in the data storing region significantly enhances the sensing margin compared to Si. Additionally, the proposed structure is shown to offer advantages over the conventional structure in terms of current variation.https://ieeexplore.ieee.org/document/10937212/One-transistor dynamic random-access memorymulti-level cellband-to-band tunnelingSi/SiGe heterojunctionTCAD simulation |
| spellingShingle | Eungi Hwang Jang Hyun Kim Sangwan Kim Garam Kim Multi-Level Cell Structure for Capacitor-Less 1T DRAM With SiGe-Based Separated Data Storing Regions IEEE Access One-transistor dynamic random-access memory multi-level cell band-to-band tunneling Si/SiGe heterojunction TCAD simulation |
| title | Multi-Level Cell Structure for Capacitor-Less 1T DRAM With SiGe-Based Separated Data Storing Regions |
| title_full | Multi-Level Cell Structure for Capacitor-Less 1T DRAM With SiGe-Based Separated Data Storing Regions |
| title_fullStr | Multi-Level Cell Structure for Capacitor-Less 1T DRAM With SiGe-Based Separated Data Storing Regions |
| title_full_unstemmed | Multi-Level Cell Structure for Capacitor-Less 1T DRAM With SiGe-Based Separated Data Storing Regions |
| title_short | Multi-Level Cell Structure for Capacitor-Less 1T DRAM With SiGe-Based Separated Data Storing Regions |
| title_sort | multi level cell structure for capacitor less 1t dram with sige based separated data storing regions |
| topic | One-transistor dynamic random-access memory multi-level cell band-to-band tunneling Si/SiGe heterojunction TCAD simulation |
| url | https://ieeexplore.ieee.org/document/10937212/ |
| work_keys_str_mv | AT eungihwang multilevelcellstructureforcapacitorless1tdramwithsigebasedseparateddatastoringregions AT janghyunkim multilevelcellstructureforcapacitorless1tdramwithsigebasedseparateddatastoringregions AT sangwankim multilevelcellstructureforcapacitorless1tdramwithsigebasedseparateddatastoringregions AT garamkim multilevelcellstructureforcapacitorless1tdramwithsigebasedseparateddatastoringregions |