ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures
Embedded video applications are now involved in sophisticated transportation systems like autonomous vehicles and driver assistance systems. As silicon capacity increases, the design productivity gap grows up for the current available design tools. Hence, high-level synthesis (HLS) tools emerged in...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2019-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2019/4298013 |
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| author | Karim M. A. Ali Rabie Ben Atitallah Abdessamad Ait El Cadi Nizar Fakhfakh Jean-Luc Dekeyser |
| author_facet | Karim M. A. Ali Rabie Ben Atitallah Abdessamad Ait El Cadi Nizar Fakhfakh Jean-Luc Dekeyser |
| author_sort | Karim M. A. Ali |
| collection | DOAJ |
| description | Embedded video applications are now involved in sophisticated transportation systems like autonomous vehicles and driver assistance systems. As silicon capacity increases, the design productivity gap grows up for the current available design tools. Hence, high-level synthesis (HLS) tools emerged in order to reduce that gap by shifting the design efforts to higher abstraction levels. In this paper, we present ViPar as a tool for exploring different video processing architectures at higher design level. First, we proposed a parametrizable parallel architectural model dedicated for video applications. Second, targeting this architectural model, we developed ViPar tool with two main features: (1) An empirical model was introduced to estimate the power consumption based on hardware utilization and operating frequency. In addition to that, we derived the equations for estimating the hardware utilization and execution time for each design point during the space exploration process. (2) By defining the main characteristics of the parallel video architecture like parallelism level, the number of input/output ports, the pixel distribution pattern, and so on, ViPar tool can automatically generate the dedicated architecture for hardware implementation. In the experimental validation, we used ViPar tool to generate automatically an efficient hardware implementation for a Multiwindow Sum of Absolute Difference stereo matching algorithm on Xilinx Zynq ZC706 board. We succeeded to increase the design productivity by converging rapidly to the appropriate designs that fit with our system constraints in terms of power consumption, hardware utilization, and frame execution time. |
| format | Article |
| id | doaj-art-0ad5bcc62ed044d5913ef129c3815ed1 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2019-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-0ad5bcc62ed044d5913ef129c3815ed12025-02-03T01:03:21ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092019-01-01201910.1155/2019/42980134298013ViPar: High-Level Design Space Exploration for Parallel Video Processing ArchitecturesKarim M. A. Ali0Rabie Ben Atitallah1Abdessamad Ait El Cadi2Nizar Fakhfakh3Jean-Luc Dekeyser4LAMIH, Polytechnic University of Hauts-de-France, Valenciennes, FranceComputer Science Department, University of Galatasaray, Istanbul, TurkeyLAMIH, Polytechnic University of Hauts-de-France, Valenciennes, FranceNAVYA Company, Villeurbanne, FranceCRIStAL, University of Lille1, Villeneuve-d’Ascq, FranceEmbedded video applications are now involved in sophisticated transportation systems like autonomous vehicles and driver assistance systems. As silicon capacity increases, the design productivity gap grows up for the current available design tools. Hence, high-level synthesis (HLS) tools emerged in order to reduce that gap by shifting the design efforts to higher abstraction levels. In this paper, we present ViPar as a tool for exploring different video processing architectures at higher design level. First, we proposed a parametrizable parallel architectural model dedicated for video applications. Second, targeting this architectural model, we developed ViPar tool with two main features: (1) An empirical model was introduced to estimate the power consumption based on hardware utilization and operating frequency. In addition to that, we derived the equations for estimating the hardware utilization and execution time for each design point during the space exploration process. (2) By defining the main characteristics of the parallel video architecture like parallelism level, the number of input/output ports, the pixel distribution pattern, and so on, ViPar tool can automatically generate the dedicated architecture for hardware implementation. In the experimental validation, we used ViPar tool to generate automatically an efficient hardware implementation for a Multiwindow Sum of Absolute Difference stereo matching algorithm on Xilinx Zynq ZC706 board. We succeeded to increase the design productivity by converging rapidly to the appropriate designs that fit with our system constraints in terms of power consumption, hardware utilization, and frame execution time.http://dx.doi.org/10.1155/2019/4298013 |
| spellingShingle | Karim M. A. Ali Rabie Ben Atitallah Abdessamad Ait El Cadi Nizar Fakhfakh Jean-Luc Dekeyser ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures International Journal of Reconfigurable Computing |
| title | ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures |
| title_full | ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures |
| title_fullStr | ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures |
| title_full_unstemmed | ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures |
| title_short | ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures |
| title_sort | vipar high level design space exploration for parallel video processing architectures |
| url | http://dx.doi.org/10.1155/2019/4298013 |
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