VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders
The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly p...
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2012-01-01
|
| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2012/614259 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832556793778143232 |
|---|---|
| author | Georgios Passas Steven Freear |
| author_facet | Georgios Passas Steven Freear |
| author_sort | Georgios Passas |
| collection | DOAJ |
| description | The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO) unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures. |
| format | Article |
| id | doaj-art-0ac372ac704d4f30970a5b2e2cb465cf |
| institution | Kabale University |
| issn | 2090-0147 2090-0155 |
| language | English |
| publishDate | 2012-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-0ac372ac704d4f30970a5b2e2cb465cf2025-02-03T05:44:18ZengWileyJournal of Electrical and Computer Engineering2090-01472090-01552012-01-01201210.1155/2012/614259614259VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code DecodersGeorgios Passas0Steven Freear1School of Electronic and Electrical Engineering, University of Leeds, Leeds LS2 9JT, UKSchool of Electronic and Electrical Engineering, University of Leeds, Leeds LS2 9JT, UKThe VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO) unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.http://dx.doi.org/10.1155/2012/614259 |
| spellingShingle | Georgios Passas Steven Freear VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders Journal of Electrical and Computer Engineering |
| title | VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders |
| title_full | VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders |
| title_fullStr | VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders |
| title_full_unstemmed | VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders |
| title_short | VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders |
| title_sort | vlsi architectures for sliding window based space time turbo trellis code decoders |
| url | http://dx.doi.org/10.1155/2012/614259 |
| work_keys_str_mv | AT georgiospassas vlsiarchitecturesforslidingwindowbasedspacetimeturbotrelliscodedecoders AT stevenfreear vlsiarchitecturesforslidingwindowbasedspacetimeturbotrelliscodedecoders |