Design of WTB Communication Board Based on FPGA+CPCI
To improve reliability and efficiency of the gateway effectively, a framework composed by FPGA+CPCI control chip was proposed. Based on the hardware design of WTB physical layer and CPCI drive interface, data transceiver of medium attachment unit (MAU) and the timing control of the local bus were in...
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| Format: | Article |
| Language: | zho |
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Editorial Department of Electric Drive for Locomotives
2014-01-01
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| Series: | 机车电传动 |
| Subjects: | |
| Online Access: | http://edl.csrzic.com/thesisDetails#10.13890/j.issn.1000-128x.2014.04.008 |
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| _version_ | 1850142573862060032 |
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| author | TIAN Yuan WANG Li-De YAN Xiang SHEN Ping |
| author_facet | TIAN Yuan WANG Li-De YAN Xiang SHEN Ping |
| author_sort | TIAN Yuan |
| collection | DOAJ |
| description | To improve reliability and efficiency of the gateway effectively, a framework composed by FPGA+CPCI control chip was proposed. Based on the hardware design of WTB physical layer and CPCI drive interface, data transceiver of medium attachment unit (MAU) and the timing control of the local bus were introduced in emphasis. According to the standard IEC61375-1, Manchester codec and the data transmission of local bus were realized by introducing finite state machine (FSM), and data read-write of FPGA to CPCI bus was accomplished by state machine transition. Finally, these designs were tested and verified in Quartus II simulation environment, and the results meet the requirements of IEC61375 for frames and timing constraints of local control signals in PCI9030 data book. |
| format | Article |
| id | doaj-art-09b9acb6a82e4372a96ba3da33de1a8c |
| institution | OA Journals |
| issn | 1000-128X |
| language | zho |
| publishDate | 2014-01-01 |
| publisher | Editorial Department of Electric Drive for Locomotives |
| record_format | Article |
| series | 机车电传动 |
| spelling | doaj-art-09b9acb6a82e4372a96ba3da33de1a8c2025-08-20T02:29:02ZzhoEditorial Department of Electric Drive for Locomotives机车电传动1000-128X2014-01-01283220908507Design of WTB Communication Board Based on FPGA+CPCITIAN YuanWANG Li-DeYAN XiangSHEN PingTo improve reliability and efficiency of the gateway effectively, a framework composed by FPGA+CPCI control chip was proposed. Based on the hardware design of WTB physical layer and CPCI drive interface, data transceiver of medium attachment unit (MAU) and the timing control of the local bus were introduced in emphasis. According to the standard IEC61375-1, Manchester codec and the data transmission of local bus were realized by introducing finite state machine (FSM), and data read-write of FPGA to CPCI bus was accomplished by state machine transition. Finally, these designs were tested and verified in Quartus II simulation environment, and the results meet the requirements of IEC61375 for frames and timing constraints of local control signals in PCI9030 data book.http://edl.csrzic.com/thesisDetails#10.13890/j.issn.1000-128x.2014.04.008CPCI busWTB (wire train bus)FSM (finite state machine)local bus |
| spellingShingle | TIAN Yuan WANG Li-De YAN Xiang SHEN Ping Design of WTB Communication Board Based on FPGA+CPCI 机车电传动 CPCI bus WTB (wire train bus) FSM (finite state machine) local bus |
| title | Design of WTB Communication Board Based on FPGA+CPCI |
| title_full | Design of WTB Communication Board Based on FPGA+CPCI |
| title_fullStr | Design of WTB Communication Board Based on FPGA+CPCI |
| title_full_unstemmed | Design of WTB Communication Board Based on FPGA+CPCI |
| title_short | Design of WTB Communication Board Based on FPGA+CPCI |
| title_sort | design of wtb communication board based on fpga cpci |
| topic | CPCI bus WTB (wire train bus) FSM (finite state machine) local bus |
| url | http://edl.csrzic.com/thesisDetails#10.13890/j.issn.1000-128x.2014.04.008 |
| work_keys_str_mv | AT tianyuan designofwtbcommunicationboardbasedonfpgacpci AT wanglide designofwtbcommunicationboardbasedonfpgacpci AT yanxiang designofwtbcommunicationboardbasedonfpgacpci AT shenping designofwtbcommunicationboardbasedonfpgacpci |