Memristor‐transistor hybrid ternary content addressable memory using ternary memristive memory cell
Abstract A memristor‐transistor hybrid ternary content addressable memory (MTCAM) with a memristor‐based ternary memory cell is proposed. New emerging devices like memristors have recently been explored to overcome the limitations of CMOS‐based memory circuits. The memristor is used as a binary memo...
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| Format: | Article |
| Language: | English |
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Wiley
2021-10-01
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| Series: | IET Circuits, Devices and Systems |
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| Online Access: | https://doi.org/10.1049/cds2.12057 |
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| author | Masoodur Rahman Khan ABM Harun‐ur Rashid |
| author_facet | Masoodur Rahman Khan ABM Harun‐ur Rashid |
| author_sort | Masoodur Rahman Khan |
| collection | DOAJ |
| description | Abstract A memristor‐transistor hybrid ternary content addressable memory (MTCAM) with a memristor‐based ternary memory cell is proposed. New emerging devices like memristors have recently been explored to overcome the limitations of CMOS‐based memory circuits. The memristor is used as a binary memory cell in these MTCAM designs to replace a CMOS‐based memory cell. This proposed design used a memristor as a ternary memory cell by exploiting its variable resistance characteristics. The associated wiring is reduced almost by a factor of 2 as a ternary cell is used instead of two binary cells. Area efficiency is further enhanced as the MTCAM cell is comprised of two transistors and two memristors (2T2M). A segmentation technique of match line along with a robust write/search operation method is presented to enhance the search speed of the proposed MTCAM. Simulation based on a mathematical model of memristor is presented and analysed using 65 nm TSMC MOS model parameters. Corner simulations and Monte Carlo simulations are carried out to substantiate the robustness of the design against process variation. Simulation results show the worst search delay of 0.75 ns and the energy/bit/search of 0.866 fJ for the 128 × 128 bit MTCAM. |
| format | Article |
| id | doaj-art-04ddb38e0f774a49a1eb4968200a4ab4 |
| institution | Kabale University |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2021-10-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-04ddb38e0f774a49a1eb4968200a4ab42025-02-03T06:47:36ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982021-10-0115761962910.1049/cds2.12057Memristor‐transistor hybrid ternary content addressable memory using ternary memristive memory cellMasoodur Rahman Khan0ABM Harun‐ur Rashid1Department of Electrical and Electronic Engineering Bangladesh University of Engineering and Technology Dhaka BangladeshDepartment of Electrical and Electronic Engineering Bangladesh University of Engineering and Technology Dhaka BangladeshAbstract A memristor‐transistor hybrid ternary content addressable memory (MTCAM) with a memristor‐based ternary memory cell is proposed. New emerging devices like memristors have recently been explored to overcome the limitations of CMOS‐based memory circuits. The memristor is used as a binary memory cell in these MTCAM designs to replace a CMOS‐based memory cell. This proposed design used a memristor as a ternary memory cell by exploiting its variable resistance characteristics. The associated wiring is reduced almost by a factor of 2 as a ternary cell is used instead of two binary cells. Area efficiency is further enhanced as the MTCAM cell is comprised of two transistors and two memristors (2T2M). A segmentation technique of match line along with a robust write/search operation method is presented to enhance the search speed of the proposed MTCAM. Simulation based on a mathematical model of memristor is presented and analysed using 65 nm TSMC MOS model parameters. Corner simulations and Monte Carlo simulations are carried out to substantiate the robustness of the design against process variation. Simulation results show the worst search delay of 0.75 ns and the energy/bit/search of 0.866 fJ for the 128 × 128 bit MTCAM.https://doi.org/10.1049/cds2.12057CMOS memory circuitscontent‐addressable storageintegrated circuit designMonte Carlo methodsmemristor circuits |
| spellingShingle | Masoodur Rahman Khan ABM Harun‐ur Rashid Memristor‐transistor hybrid ternary content addressable memory using ternary memristive memory cell IET Circuits, Devices and Systems CMOS memory circuits content‐addressable storage integrated circuit design Monte Carlo methods memristor circuits |
| title | Memristor‐transistor hybrid ternary content addressable memory using ternary memristive memory cell |
| title_full | Memristor‐transistor hybrid ternary content addressable memory using ternary memristive memory cell |
| title_fullStr | Memristor‐transistor hybrid ternary content addressable memory using ternary memristive memory cell |
| title_full_unstemmed | Memristor‐transistor hybrid ternary content addressable memory using ternary memristive memory cell |
| title_short | Memristor‐transistor hybrid ternary content addressable memory using ternary memristive memory cell |
| title_sort | memristor transistor hybrid ternary content addressable memory using ternary memristive memory cell |
| topic | CMOS memory circuits content‐addressable storage integrated circuit design Monte Carlo methods memristor circuits |
| url | https://doi.org/10.1049/cds2.12057 |
| work_keys_str_mv | AT masoodurrahmankhan memristortransistorhybridternarycontentaddressablememoryusingternarymemristivememorycell AT abmharunurrashid memristortransistorhybridternarycontentaddressablememoryusingternarymemristivememorycell |