A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip
Runtime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world. The runtime exchange of modules, implemented on a reconfigurable hardware, affects the instruction flow (e.g., in reconfigurable instruction set...
Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2009-01-01
|
| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2009/395018 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832563539677544448 |
|---|---|
| author | Diana Göhringer Thomas Perschke Michael Hübner Jürgen Becker |
| author_facet | Diana Göhringer Thomas Perschke Michael Hübner Jürgen Becker |
| author_sort | Diana Göhringer |
| collection | DOAJ |
| description | Runtime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world. The runtime exchange of modules, implemented on a reconfigurable hardware, affects the instruction flow (e.g., in reconfigurable instruction set processors) or the data flow, which has a strong impact on the performance of an application. Furthermore, the choice of a certain processor architecture related to the class of target applications is a crucial point in application development. A simple example is the domain of high-performance computing applications found in meteorology or high-energy physics, where vector processors are the optimal choice. A classification scheme for computer systems was provided in 1966 by Flynn where single/multiple data and instruction streams were combined to four types of architectures. This classification is now used as a foundation for an extended classification scheme including runtime adaptivity as further degree of freedom for processor architecture design. The developed scheme is validated by a multiprocessor system implemented on reconfigurable hardware as well as by a classification of existing static and reconfigurable processor systems. |
| format | Article |
| id | doaj-art-04c134b73bef487eabf75276bc18d492 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2009-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-04c134b73bef487eabf75276bc18d4922025-02-03T01:13:08ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092009-01-01200910.1155/2009/395018395018A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-ChipDiana Göhringer0Thomas Perschke1Michael Hübner2Jürgen Becker3FGAN-FOM, Research Institute for Optronics and Pattern Recognition, 76275 Ettlingen, GermanyFGAN-FOM, Research Institute for Optronics and Pattern Recognition, 76275 Ettlingen, GermanyFakultät für Elektrotechnik und Informationstechnik, Universität Karlsruhe, Institut für Technik der Informationsverarbeitung (ITIV), 76131 Karlsruhe, GermanyFakultät für Elektrotechnik und Informationstechnik, Universität Karlsruhe, Institut für Technik der Informationsverarbeitung (ITIV), 76131 Karlsruhe, GermanyRuntime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world. The runtime exchange of modules, implemented on a reconfigurable hardware, affects the instruction flow (e.g., in reconfigurable instruction set processors) or the data flow, which has a strong impact on the performance of an application. Furthermore, the choice of a certain processor architecture related to the class of target applications is a crucial point in application development. A simple example is the domain of high-performance computing applications found in meteorology or high-energy physics, where vector processors are the optimal choice. A classification scheme for computer systems was provided in 1966 by Flynn where single/multiple data and instruction streams were combined to four types of architectures. This classification is now used as a foundation for an extended classification scheme including runtime adaptivity as further degree of freedom for processor architecture design. The developed scheme is validated by a multiprocessor system implemented on reconfigurable hardware as well as by a classification of existing static and reconfigurable processor systems.http://dx.doi.org/10.1155/2009/395018 |
| spellingShingle | Diana Göhringer Thomas Perschke Michael Hübner Jürgen Becker A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip International Journal of Reconfigurable Computing |
| title | A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip |
| title_full | A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip |
| title_fullStr | A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip |
| title_full_unstemmed | A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip |
| title_short | A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip |
| title_sort | taxonomy of reconfigurable single multiprocessor systems on chip |
| url | http://dx.doi.org/10.1155/2009/395018 |
| work_keys_str_mv | AT dianagohringer ataxonomyofreconfigurablesinglemultiprocessorsystemsonchip AT thomasperschke ataxonomyofreconfigurablesinglemultiprocessorsystemsonchip AT michaelhubner ataxonomyofreconfigurablesinglemultiprocessorsystemsonchip AT jurgenbecker ataxonomyofreconfigurablesinglemultiprocessorsystemsonchip AT dianagohringer taxonomyofreconfigurablesinglemultiprocessorsystemsonchip AT thomasperschke taxonomyofreconfigurablesinglemultiprocessorsystemsonchip AT michaelhubner taxonomyofreconfigurablesinglemultiprocessorsystemsonchip AT jurgenbecker taxonomyofreconfigurablesinglemultiprocessorsystemsonchip |