Critical Gates Identification for Fault-Tolerant Design in Math Circuits
Hardware redundancy at different levels of design is a common fault mitigation technique, which is well known for its efficiency to the detriment of area overhead. In order to reduce this drawback, several fault-tolerant techniques have been proposed in literature to find a good trade-off. In this p...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2017-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2017/5684902 |
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