Critical Gates Identification for Fault-Tolerant Design in Math Circuits
Hardware redundancy at different levels of design is a common fault mitigation technique, which is well known for its efficiency to the detriment of area overhead. In order to reduce this drawback, several fault-tolerant techniques have been proposed in literature to find a good trade-off. In this p...
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| Format: | Article |
| Language: | English |
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Wiley
2017-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2017/5684902 |
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| author | Tian Ban Gutemberg G. S. Junior |
| author_facet | Tian Ban Gutemberg G. S. Junior |
| author_sort | Tian Ban |
| collection | DOAJ |
| description | Hardware redundancy at different levels of design is a common fault mitigation technique, which is well known for its efficiency to the detriment of area overhead. In order to reduce this drawback, several fault-tolerant techniques have been proposed in literature to find a good trade-off. In this paper, critical constituent gates in math circuits are detected and graded based on the impact of an error in the output of a circuit. These critical gates should be hardened first under the area constraint of design criteria. Indeed, output bits considered crucial to a system receive higher priorities to be protected, reducing the occurrence of critical errors. The 74283 fast adder is used as an example to illustrate the feasibility and efficiency of the proposed approach. |
| format | Article |
| id | doaj-art-03e4273e5fa74e18a1046bf2a5fb77be |
| institution | Kabale University |
| issn | 2090-0147 2090-0155 |
| language | English |
| publishDate | 2017-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-03e4273e5fa74e18a1046bf2a5fb77be2025-02-03T01:00:35ZengWileyJournal of Electrical and Computer Engineering2090-01472090-01552017-01-01201710.1155/2017/56849025684902Critical Gates Identification for Fault-Tolerant Design in Math CircuitsTian Ban0Gutemberg G. S. Junior1School of Electronic and Optical Engineering, Nanjing University of Science and Technology, Nanjing 210094, ChinaDepartment of Communications and Electronics, Institut Mines-Télécom, Télécom ParisTech, 75013 Paris, FranceHardware redundancy at different levels of design is a common fault mitigation technique, which is well known for its efficiency to the detriment of area overhead. In order to reduce this drawback, several fault-tolerant techniques have been proposed in literature to find a good trade-off. In this paper, critical constituent gates in math circuits are detected and graded based on the impact of an error in the output of a circuit. These critical gates should be hardened first under the area constraint of design criteria. Indeed, output bits considered crucial to a system receive higher priorities to be protected, reducing the occurrence of critical errors. The 74283 fast adder is used as an example to illustrate the feasibility and efficiency of the proposed approach.http://dx.doi.org/10.1155/2017/5684902 |
| spellingShingle | Tian Ban Gutemberg G. S. Junior Critical Gates Identification for Fault-Tolerant Design in Math Circuits Journal of Electrical and Computer Engineering |
| title | Critical Gates Identification for Fault-Tolerant Design in Math Circuits |
| title_full | Critical Gates Identification for Fault-Tolerant Design in Math Circuits |
| title_fullStr | Critical Gates Identification for Fault-Tolerant Design in Math Circuits |
| title_full_unstemmed | Critical Gates Identification for Fault-Tolerant Design in Math Circuits |
| title_short | Critical Gates Identification for Fault-Tolerant Design in Math Circuits |
| title_sort | critical gates identification for fault tolerant design in math circuits |
| url | http://dx.doi.org/10.1155/2017/5684902 |
| work_keys_str_mv | AT tianban criticalgatesidentificationforfaulttolerantdesigninmathcircuits AT gutemberggsjunior criticalgatesidentificationforfaulttolerantdesigninmathcircuits |