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    A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction

    A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction by Yu-Ping Huang, Yu-Sian Lu, Wei-Zen Chen

    Published 2024-01-01
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