Showing 1 - 3 results of 3 for search 'Saeroonter Oh', query time: 0.01s Refine Results
  1. 1
    Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

    Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach by Ji Hwan Lee, Kihwan Kim, Kyungjin Rim, Soogine Chong, Hyunbo Cho, Saeroonter Oh

    Published 2024-01-01
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  2. 2
    Enhancing InGaZnO transistor current through high-κ dielectrics and interface trap extraction using single-pulse charge pumping

    Enhancing InGaZnO transistor current through high-κ dielectrics and interface trap extraction using single-pulse charge pumping by JaeHyeong Park, Hyo-Bae Kim, Sang Min Yu, Kihwan Kim, Ju Heyuck Baeck, Jiyong Noh, Kwon-Shik Park, Soo-Young Yoon, Ji-Hoon Ahn, Saeroonter Oh

    Published 2025-07-01
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  3. 3
    Revisiting the role of oxidation in stable and high-performance lead-free perovskite-IGZO junction field-effect transistors

    Revisiting the role of oxidation in stable and high-performance lead-free perovskite-IGZO junction field-effect transistors by Seonkwon Kim, Su Hyun Kim, Hui Ung Hwang, Jeongmin Kim, Jeong Won Kim, In Cheol Kwak, Byeongjae Kang, Seungjae Lee, Sae Byeok Jo, Du Yeol Ryu, Hyunjung Kim, Jae-Min Myoung, Moon Sung Kang, Saeroonter Oh, Jeong Ho Cho

    Published 2025-08-01
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