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    Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs

    Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs by Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini

    Published 2009-01-01
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  2. 2
    Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization

    Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization by Mountassar Maamoun, Adnane Hassani, Samir Dahmani, Hocine Ait Saadi, Ghania Zerari, Noureddine Chabini, Rachid Beguenane

    Published 2021-08-01
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