Showing 1 - 11 results of 11 for search 'L. D. Cheremisinova', query time: 0.01s Refine Results
  1. 1
    TESTS GENERATION FOR POWER CONSUMPTION ESTIMATION OF SEQUENTIAL CIRCUITS

    TESTS GENERATION FOR POWER CONSUMPTION ESTIMATION OF SEQUENTIAL CIRCUITS by L. D. Cheremisinova

    Published 2017-12-01
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  2. 2
    MULTIPLE FOLDING OF REGULAR STRUCTURES VIA SOLVING LOGIC EQUATIONS

    MULTIPLE FOLDING OF REGULAR STRUCTURES VIA SOLVING LOGIC EQUATIONS by L. D. Cheremisinova

    Published 2016-09-01
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  3. 3
    Extraction of logical networks during decompiling transistor-level CMOS circuit descriptions

    Extraction of logical networks during decompiling transistor-level CMOS circuit descriptions by D. I. Cheremisinov, L. D. Cheremisinova

    Published 2024-09-01
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  4. 4
    POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS

    POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS by D. I. Cheremisinov, L. D. Cheremisinova

    Published 2016-10-01
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  5. 5
    ANALYSIS OF EFFECTIVENESS OF TECHNOLOGY INDEPENDENT OPTIMIZATION OF CMOS CIRCUIT FUNCTIONAL DESCRIPTIONS

    ANALYSIS OF EFFECTIVENESS OF TECHNOLOGY INDEPENDENT OPTIMIZATION OF CMOS CIRCUIT FUNCTIONAL DESCRIPTIONS by N. A. Kirienko, L. D. Cheremisinova

    Published 2016-09-01
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  6. 6
    Simulation of discrete control systems with parallelism of behavior

    Simulation of discrete control systems with parallelism of behavior by D. I. Cheremisinov, L. D. Cheremisinova

    Published 2023-12-01
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  7. 7
    Logical gates recognition in a flat transistor circuit

    Logical gates recognition in a flat transistor circuit by D. I. Cheremisinov, L. D. Cheremisinova

    Published 2021-12-01
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  8. 8
    Redesigning CMOS VLSI using Yosys synthesis tool

    Redesigning CMOS VLSI using Yosys synthesis tool by D. I. Cheremisinov, L. D. Cheremisinova

    Published 2025-03-01
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  9. 9
    Canonization of graphs during transistor circuits decompilation

    Canonization of graphs during transistor circuits decompilation by D. I. Cheremisinov, L. D. Cheremisinova

    Published 2022-09-01
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  10. 10
    Verification of systems with behavior parallelism on the basis of the graph of reachable states

    Verification of systems with behavior parallelism on the basis of the graph of reachable states by Yu. V. Pottosin, V. I. Romanov, L. D. Cheremisinova

    Published 2019-06-01
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  11. 11
    ON SCIENCE HERITAGE OF CORRESPONDING MEMBER А.D. ZAKREVSKIJ

    ON SCIENCE HERITAGE OF CORRESPONDING MEMBER А.D. ZAKREVSKIJ by P. N. Bibilo, Yu. V. Pottosin, L. D. Cheremisinova

    Published 2017-03-01
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